ARTERY AT32F403ACGT7
The AT32F403A series is based on the high-performance ARM®Cortex®-M4 32-bit RISC core operating at a frequency of up to 240 MHz. The Cortex®-M4 core features a Floating point unit (FPU) single precision which supports all ARM® single-precision data processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances application security.| Part No. | AT32F403ACGT7 |
|---|---|
| Datasheet | AT32F403ACGT7 Download |
| Manufacturer | ARTERY |
| Description | 32-bit MCU+FPU |
| Buy | Stock & Price |
AT32F403A Series Datasheet ARM®-based 32-bit Cortex®-M4 MCU+FPU with 256 to 1024 KB Flash, sLib, 17 timers, 3 ADCs, 20 communication interfaces (USBFS) Feature
● Core: ARM® 32-bit Cortex®-M4 CPU with FPU − 240 MHz maximum frequency, with a memory protection unit (MPU), single-cycle multiplication and hardware division − Floating point unit (FPU) and − DSP instructions
● Memories − 256 to 1024 KBytes of internal Flash memory − sLib: configurable part of main Flash set as a libruary area with code excutable but secured, non-readable − SPIM interface: Extra interfacing up to 16 Mbytes of the external SPI Flash (as instruction/data memory) − Up to 96+128 KBytes of SRAM − External memory controller (XMC) with 16bit data bus. Supports multiplexed PSRAM/NOR and NAND memories
● XMC as LCD parallel interface, compatible with 8080/6800 modes
● Power control (PWC) − 2.6 to 3.6 V application supply − Power on reset (POR), low voltage reset (LVR), and power voltage monitoring (PVM) − Low power mode...
● Core: ARM® 32-bit Cortex®-M4 CPU with FPU − 240 MHz maximum frequency, with a memory protection unit (MPU), single-cycle multiplication and hardware division − Floating point unit (FPU) and − DSP instructions
● Memories − 256 to 1024 KBytes of internal Flash memory − sLib: configurable part of main Flash set as a libruary area with code excutable but secured, non-readable − SPIM interface: Extra interfacing up to 16 Mbytes of the external SPI Flash (as instruction/data memory) − Up to 96+128 KBytes of SRAM − External memory controller (XMC) with 16bit data bus. Supports multiplexed PSRAM/NOR and NAND memories
● XMC as LCD parallel interface, compatible with 8080/6800 modes
● Power control (PWC) − 2.6 to 3.6 V application supply − Power on reset (POR), low voltage reset (LVR), and power voltage monitoring (PVM) − Low power mode...
