ASI AS4LC4M4883C
The AS4LC4M4 is a randomly accessed solid-state memory containing 16,777,216 bits organized in a x4 configuration. The AS4LC4M4 ?R?A/S is used to latch the first 11 bits and ?C?A/S the latter 11 bits.| Part No. | AS4LC4M4883C |
|---|---|
| Datasheet | AS4LC4M4883C Download |
| Manufacturer |  ASI |
| Description | EDO PAGE MODE |
| Buy | Stock & Price |
FEATURES
● Industry-standard x4 pinout, timing, functions and packages● High-performance CMOS silicon-gate process
● Single +3.3V ± 0.3V power supply
● Low power, 1mW standby; 150mW active, typical
● All inputs, outputs and clocks are TTL-compatible
● Refresh modes: ?R?A/S ONLY, ?C?A/S-BEFORE-?R?A/S (CBR) HIDDEN
● 2,048-cycle (11 row-, 11 column-addresses)
● Extended Data-Out (EDO) PAGE access cycle
● 5V-tolerant I/Os (5.5V maximum VIH level) VCC DQ1 DQ2 /W/E /R/A/S NC A10 A0 A1 A2 A3 VCC OPTIONS
● Timing 60ns access (Contact Factory) 70ns acess 80ns access
● Packages Ceramic SOJ Ceramic LCC Ceramic Gull Wing MARKING -6 -7 -8 ECJ EC ECG No. 505 No. 212 No. 603 KEY TIMING PARAMETERS SPEED -6 -7 -8 tRC 110ns 130ns 150ns tRAC 60ns 70ns 80ns tPC 30ns 35ns 40ns tAA 30ns 35ns 40ns tCAC 15ns 18ns 20ns tCAS 12ns 15ns 20ns
GENERAL DESCRIPTION
READ and WRITE cycles are selected with the ? W / E input. A logic HIGH on ?W/E dictates READ mode while a logic LOW on ?W/E dictates WRITE mode. During a WRITE cycle, data-in (D) is latched by the falling edge of ?W/E or ?C?A/S, whichever occurs last.
