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AS4LC4M4883C - EDO PAGE MODE

Description

The AS4LC4M4 is a randomly accessed solid-state memory containing 16,777,216 bits organized in a x4 configuration.

The AS4LC4M4 ?R?A/S is used to latch the first 11 bits and ?C?A/S the latter 11 bits.

READ and WRITE cycles are selected with the ?

Features

  • Industry-standard x4 pinout, timing, functions and packages.
  • High-performance CMOS silicon-gate process.
  • Single +3.3V ± 0.3V power supply.
  • Low power, 1mW standby; 150mW active, typical.
  • All inputs, outputs and clocks are TTL-compatible.
  • Refresh modes: ?R?A/S ONLY, ?C?A/S-BEFORE-?R?A/S (CBR) HIDDEN.
  • 2,048-cycle (11 row-, 11 column-addresses).
  • Extended Data-Out (EDO) PAGE access cycle.
  • 5V-tolerant I/Os (5.5V maximum.

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Datasheet preview – AS4LC4M4883C

Datasheet Details

Part number AS4LC4M4883C
Manufacturer ASI
File Size 213.74 KB
Description EDO PAGE MODE
Datasheet download datasheet AS4LC4M4883C Datasheet
Additional preview pages of the AS4LC4M4883C datasheet.

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Other Datasheets by ASI

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    www.DataSheet4U.com AUSTIN SEMICONDUCTOR, INC. AS4LC4M4 883C 4 MEG x 4 DRAM DRAM AVAILABLE IN MILITARY SPECIFICATIONS • MIL-STD-883 • SMD Planned 4 MEG x 4 DRAM 3.3V, EDO PAGE MODE PIN ASSIGNMENT (Top View) 24/28-Pin 1 1 2 2 3 3 4 4 5 5 6 6 9 8 10 9 11 10 12 11 13 12 14 13 28 26 27 25 26 24 25 23 24 22 23 21 20 19 19 18 18 17 17 16 16 15 15 14 VSS DQ4 DQ3 /C/A/S /O/E A9 A8 A7 A6 A5 A4 Vss FEATURES • Industry-standard x4 pinout, timing, functions and packages • High-performance CMOS silicon-gate process • Single +3.3V ± 0.
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