MT5C1005 Overview
The Austin Semiconductor SRAM family employs high-speed, low power CMOS designs fabricated using doublelayer metal, double-layer polysilicon technology. For flexibility in high-speed memory applications, ASI offers chip enable (CE) and output enable (OE) capability. These enhancements can place the outputs in High-Z for additional flexibility in system design.
MT5C1005 Key Features
- High Speed: 20, 25, 35, and 45 Battery Backup: 2V data retention Low power standby High-performance, low-power CMOS doub
- Single +5V (+10%) Power Supply
- Easy memory expansion with CE and OE options
- All inputs and outputs are TTL patible
- 20 -25 -35 -45 -55- -70
- Package(s) Ceramic DIP (400 mil) C Ceramic Quad LCC (contact factory) ECW Ceramic LCC EC Ceramic Flatpack F Ceramic SOJ
- Operating Temperature Ranges Industrial (-40oC to +85oC) IT Military (-55oC to +125oC) XT
- 2V data retention/low power L
MT5C1005 Applications
- Electrical characteristics identical to those provided for the 45ns access devices
