FEATURES
Document No.: AX88196B_106/01/13/12 High-performance non-PCI local bus Support 8/16-bit local CPU interfaces include MCS-51 series, 80186 series CPU and ISA bus SRAM-like host interface (US Patent Approval), easily interfaced to most common embedded MCUs Embed 8Kx16 bits SRAM for packet buffers Support Slave-DMA to minimize CPU overhead Support burst-mode read for highest performance applications Interrupt pin with programmable Hold-off timer Single-chip Fast Ethernet controller Compatible with IEEE802.3, 802.3u standards Integrate Fast Ethernet MAC/PHY transceiver in one chip Support 10Mbps and 100Mbps data rate Support full and half duplex operations Support 10/100Mbps N-way Auto-negotiation operation Support twisted pair crossover detection and auto-correction (HP Auto-MDIX) Support IEEE 802.3x flow control for full-duplex operation Support back-pressure flow control for half-duplex operation Provide optional MII interface for external 100BASE-FX Ethernet PHY, HomePNA PHY o...
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