AX88780 Datasheet | ASIX

Features - High-performance non-PCI local bus Support back-pressure flow control for half-duplex 16/32-bit SRAM-like host interface (US Patent operation Approval) Support packet length set by software Support big/little endian data bus type Support MII interface for external Ethernet PHY Large embedded SRAM for packet buffers ¾ 32K bytes for receive buffer ¾ 8K bytes for transmit buffer and Home PNA/Home Plug PHY applications - Support Wake-on-LAN function by following events Detection of network link-up state Support IP/TCP/UDP checksum offloads Receipt of a Magic Packet Support interrupt with high or low active trigger - Support Magic Packet detection for remote wake-up mode after power- on reset - Single-chip Fast Ethernet controller - Support EEPROM interface patible with IEEE802.3, 802.3u standards - Support synchronous or asynchronous mode to host Integrated Fast Ethernet MAC/PHY transceiver in MCU one chip - Support LED pins for various network activity Support 10Mbps and 100Mbps data rate indications Support full and half duplex operations - Integrated voltage regulator from 3.3V to 2.5V Support 10/100Mbps N-way Auto-negotiation - 2.5V for core and 3.3V I/O with 5V tolerance operation - 128-pin LQFP with CMOS process, Ro HS package Support IEEE 802.3x flow control for full-duplex operation Product Description The AX88780 is a high-performance and cost-effective single-chip Fast Ethernet controller for various embedded systems including consumer electronics and home network markets that require a higher level of network connectivity. The AX88780 supports 16/32-bit SRAM-like host interface and integrates on-chip Fast Ethernet MAC and PHY, which is IEEE802.3 10Base-T and IEEE802.3u 100Base-T patible. The AX88780 supports full-duplex or half-duplex operation at 10/100Mbps speed with auto-negotiation or manual setting. The AX88780 integrates large embedded SRAM for packet buffers to acmodate high bandwidth applications and supports...