FEATURES
High-performance non-PCI local bus Support both 8 bit and 16 bit local CPU interfaces include MCS-51 series, 80186 series CPU and ISA bus SRAM-like host interface, easily interfaced to most common embedded MCUs Embed 8Kx16 bits SRAM for packet buffers Support Slave-DMA to minimize CPU overhead Support burst -mode read for hi ghest performance applications Interrupt pin with programmable Hold-off timer Single-chip Fast Ethernet controller Compatible with IEEE802.3, 802.3u standards Integrate Fast Ethernet MAC/PHY transceiver in one chip Support 10Mbps and 100Mbps data rate Support full and half duplex operations Support 10/ 100Mbps N-way Aut o-negotiation operation Support twisted pair crossover detection and auto-correction (HP Auto-MDIX) Support IEEE 802.3x flow control for full-duplex operation Support back-pressure fl ow control for half-duplex operation Document No.: AX88796B_17/08/18/07 Support VLAN match filter Support Wake-on-LAN funct ion t o reduce power by following...
ASIX
