ASIX AX88796C
Low-Power SPI or Non-PCI Ethernet Controller
FEATURES
Document No.: AX88796C/V1.14/04/15/11 High-performance non-PCI local bus Supports 8/16-bit SRAM-like host interface (US Patent Approval), easily interfaced to most common embedded MCUs; or 8/16-bit local CPU interface including MCS-51 series, Renesas series CPUs Supports Slave-DMA to minimize CPU overhead and burst mode read & write access for frame reception & transmission on SRAM-like interface for high performance applications Supports variable voltage I/O (1.8/2.5/3.3V) and programmable driving strength (8/16mA) Interrupt pin with programmable timer High-performance SPI slave interface Supports SPI slave interface for CPU with SPI master. The SPI slave interface supports SPI timing mode 0 and 3, up to 40MHz of SPI CLK, variable voltage I/O and programmable driving strength Supports optional Ready signal as flow control for SPI packet RX/TX Single-chip Fast Ethernet MAC/PHY controller Embeds 14KB SRAM for packet buffers Supports IPv4/IPv6 packet Checksum Offload Engine to r...