DESCRIPTION
First ATAN version Change RXP, RXN, TXP, TXN Change hardware Setting pin from A1 version 1. ENDC16 Swap with Dual Color setting EEPROM 0x12h bit 15.. 2. Aging hardware setting change to EEPROM 0x10h bit7. Port7 FX select change to TXER power on latch. 3. At Dual Speed mode each port support 100/10 Full/Half Separate from AT8985P data sheet 1. Remove PHY Register from Data Sheet 2. Add EEPROM read explain in Dupcol1 pin. 3. Modify LED display pin description. 1. Add eeprom register 0x11h defaulted value as 0xff00h 2. Support By-pass Mode, register 0x11h bit5 3. Support Port-Base VLAN as default setting, Registger 0x11h Bit5 4. Special address forwarding 01 80 C2 00 00 00 DA Forwarding 01 80 C2 00 00 01 DA Filtering 01 80 C2 00 00 02 ~ 01 80 C2 00 00 0F DA Forwarding 5. Support Maximum Packet size as Bypass mode : Tag packet 1522Byte, Untag packet 1522byte Non-bypass mode : Tag packet 1526byte, Untag packet 1522byte 6. CFG0 pin86 must be externally connected to GND on PCB. July/2001 0.3 Aug/2001 Sep/2001 0.4 0.9 Feb/2002 1.0 Notice: This document contains preliminary information on new products under development.
