25F512 Overview
The device is optimized for use in many industrial and mercial applications where low-power and low-voltage operation are essential. The AT25F512/1024 is available in a space-saving 8-lead JEDEC SOIC package. The AT25F512/1024 is enabled through the Chip Select pin (CS) and accessed via a 3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK).
25F512 Key Features
- Two Sectors with 32K Bytes Each (512K)
- Four Sectors with 32K Bytes Each (1M)
- 128 Pages per Sector
- Product Identification Mode
- Low-voltage Operation
- 2.7 (VCC = 2.7V to 3.6V)
- Sector Write Protection
- Write Protect (WP) Pin and Write Disable Instructions for .. both Hardware and Software Data Protection
- Self-timed Program Cycle (60 µs/Byte Typical)
- Self-timed Sector Erase Cycle (1 second/Sector Typical)