Datasheet Summary
Features
- 80C52X2 Core (6 Clocks per Instruction)
- Maximum Core Frequency 48 MHz in X1 Mode, 24MHz in X2 Mode
- Dual Data Pointer
- Full-duplex Enhanced UART (EUART)
- Three 16-bit Timer/Counters: T0, T1 and T2
- 256 Bytes of Scratchpad RAM
- 32-Kbyte On-chip Flash In-System Programming through USB or UART
- 4-Kbyte EEPROM for Boot (3-Kbyte) and Data (1-Kbyte)
- On-chip Expanded RAM (ERAM): 1024 Bytes
- USB 1.1 and 2.0 Full Speed pliant Module with Interrupt on Transfer pletion
- Endpoint 0 for Control Transfers: 32-byte FIFO
- 6 Programmable Endpoints with In or Out Directions and with Bulk, Interrupt or Isochronous Transfers
- Endpoint 1, 2, 3: 32-byte FIFO
- Endpoint 4, 5: 2 x...