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AT40K40 - 5K - 50K Gates Coprocessor FPGA

Download the AT40K40 datasheet PDF. This datasheet also covers the AT40K05 variant, as both devices belong to the same 5k - 50k gates coprocessor fpga family and are provided as variant models within a single manufacturer datasheet.

General Description

The AT40K is a family of fully PCI-compliant, SRAM-based FPGAs with distributed 10ns programmable synchronous/asynchronous, dual-port/single-port SRAM, eight global clocks, Cache Logic ability (partially or fully reconfigurable without loss of data), automatic component generators, and range in size

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (AT40K05-ATMELCorporation.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
AT40K40AL 5K - 50K Gates Coprocessor FPGA ATMEL
AT40K40LV 5K - 50K Gates Coprocessor FPGA ATMEL
AT40K05AL 5K - 50K Gates Coprocessor FPGA ATMEL
AT40K05LV 5K - 50K Gates Coprocessor FPGA ATMEL
AT40K10AL 5K - 50K Gates Coprocessor FPGA ATMEL

Other Datasheets by Atmel (now Microchip Technology)

Part Number Description
AT40K05 5K - 50K Gates Coprocessor FPGA
AT40K10 5K - 50K Gates Coprocessor FPGA
AT40K20 5K - 50K Gates Coprocessor FPGA
AT40KAL Military Reprogrammable FPGAs
AT40KEL040 Rad Hard Reprogrammable FPGAs

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
AT40K05, AT40K10, AT40K20, AT40K40 5K – 50K Gates Coprocessor FPGA with FreeRAM™ Features DATASHEET  Ultra high performance  System speeds to 100MHz  Array multipliers > 50MHz  10ns flexible SRAM  Internal tri-state capability in each cell  FreeRAM™  Flexible, single/dual port, synchronous/asynchronous 10ns SRAM  2,048 – 18,432 bits of distributed SRAM independent of logic cells  128 – 384 PCI compliant I/Os  5V capability  Programmable output drive  Fast, flexible array access facilitates pin locking  Pin-compatible with XC4000 and XC5200 FPGAs  Eight global clocks  Fast, low skew clock distribution  Programmable rising/falling edge transitions  Distributed clock shutdown capability for low power management  Global reset/asynchronous reset options  4 additional dedic