AT572D940HF Description
One plex Multiply with Dual Add/Sub per Clock Cycle or Two Multiply and Two Add/sub or Simple Scalar Operations 32-bit Integer and IEEE® 40-bit Extended Precision Floating Point Numeric Format 16-port Data Register File: 256 Registers organized in Two 128-register Banks 5-issue predicated VLIW Architecture with Orthogonal ISA, Code pression and Hardware Support for Code Efficient Software Pipeline Loops 6 Accesses...
AT572D940HF Key Features
- DIOPSIS Dual Core System Integrating an ARM926EJ-S™ ARM® Thumb® Processor