Datasheet Summary
Features
General
- High-performance, Low-power AVR® Enhanced RISC Architecture
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- 120 Powerful Instructions (Most Executed in a Single Clock Cycle) Low Power Idle and Power-down Modes Bond Pad Locations Conforming to ISO 7816-2 ESD Protection to ± 4000V Operating Ranges: 2.7V to 5.50V pliant with GSM, 3GPP and EMV 2000 Specifications Available in Wafers, Modules, and Industry-standard Packages
Memory
- 120K Bytes of ROM Program Memory
- 36K Bytes of EEPROM, Including 64 OTP Bytes and 64-byte Bit-addressable Bytes
- 1 to 128-byte Program / Erase
- 1ms Program / 1ms Erase
- Typically 500,000 Write/Erase Cycles at a Temperature of 25oC
- 10 Years Data Retention
- 3K bytes RAM...