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Features
• Incorporates the ARM7TDMI® ARM® Thumb® Processor Core
– High-performance 32-bit RISC Architecture – High-density 16-bit Instruction Set – Leader in MIPS/Watt – Embedded ICE (In-circuit Emulation) 256K Bytes of On-chip SRAM – 32-bit Data Bus, Single-clock Cycle Access 1024K Words 16-bit Flash Memory (2M bytes) – Single Voltage Read/Write, – Sector Erase Architecture – Dual-plane Organization Allows Concurrent Read and Program/Erase – Erase Suspend Capability – Low-power Operation – Data Polling, Toggle Bit and Ready/Busy End of Program Cycle Detection – Reset Input for Device Initialization – Sector Program Unlock Command – 128-bit Protection Register – Factory-programmed AT91 Flash Uploader Software Fully Programmable External Bus Interface (EBI) – Up to 8 Chip Selects, Maximum