AT91SAM7X128
AT91SAM7X128 is AT91 ARM Thumb-based Microcontrollers manufactured by Atmel.
Features
- Incorporates the ARM7TDMI® ARM® Thumb® Processor
- High-performance 32-bit RISC Architecture
- High-density 16-bit Instruction Set
- Leader in MIPS/Watt
- Embedded ICE In-circuit Emulation, Debug munication Channel Support Internal High-speed Flash
- 256 Kbytes (AT91SAM7X256) Organized in 1024 Pages of 256 Bytes
- 128 Kbytes (AT91SAM7X128) Organized in 512 Pages of 256 Bytes
- Single Cycle Access at Up to 30 MHz in Worst Case Conditions
- Prefetch Buffer Optimizing Thumb Instruction Execution at Maximum Speed
- Page Programming Time: 6 ms, Including Page Auto-erase, Full Erase Time: 15 ms
- 10,000 Write Cycles, 10-year Data Retention Capability, Sector Lock Capabilities, Flash Security Bit
- Fast Flash Programming Interface for High Volume Production Internal High-speed SRAM, Single-cycle Access at Maximum Speed
- 64 Kbytes (AT91SAM7X256)
- 32 Kbytes (AT91SAM7X128) Memory Controller (MC)
- Embedded Flash Controller, Abort Status and Misalignment Detection Reset Controller (RSTC)
- Based on Power-on Reset Cells and Low-power Factory-calibrated Brownout Detector
- Provides External Reset Signal Shaping and Reset Source Status Clock Generator (CKGR)
- Low-power RC Oscillator, 3 to 20 MHz On-chip Oscillator and one PLL Power Management Controller (PMC)
- Power Optimization Capabilities, Including Slow Clock Mode (Down to 500 Hz) and Idle Mode
- Four Programmable External Clock Signals Advanced Interrupt Controller (AIC)
- Individually Maskable, Eight-level Priority, Vectored Interrupt Sources
- Two External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected Debug Unit (DBGU)
- 2-wire UART and Support for Debug munication Channel interrupt, Programmable ICE Access Prevention Periodic Interval Timer (PIT)
- 20-bit Programmable Counter plus 12-bit Interval Counter Windowed Watchdog (WDT)
- 12-bit key-protected Programmable Counter
- Provides Reset or Interrupt Signals to the System
- Counter May Be Stopped While the Processor is in...