Datasheet Summary
Features
- prehensive Library of Standard Logic and I/O Cells
- ATC18RHA Core and I/O Cells Designed to Operate with VDD = 1.8V Sparing 0.15V as
Main Target Operating Conditions IO33 Pad Libraries Provide Interfaces to 3V Environments Memory Cells piled to the Precise Requirements of the Design EDAC Library SEU Hardened DFF’s Cold Sparring Buffers High Speed LVDS Buffers PCI Buffers Predefined Die Sizes to Acmodate Specified Packages and ESA (European Space Agency) Multi-project Wafer Services
- MQFP Package Up to 352 Pins (340 Signal Pins)
- MCGA Packages Up to 625 Pins (581 Signal Pins)
- Assurance Programs Will Allow
- Testing Flight Models to SCC B and QML Q & V
- Monitoring...