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Features
• High-performance Fully CMOS, Electrically-erasable Complex Programmable
Logic Device – 64 Macrocells – 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell – 5.0 ns Pin-to-pin Propagation Delay – Registered Operation up to 333 MHz – Enhanced Routing Resources – Optimized for 1.8V Operation – 2 I/O Banks to Facilitate Multi-voltage I/O Operation: 1.5V, 1.8V, 2.5V, 3.3V – SSTL2-1 and SSTL3-1 Receiver In-System Programming (ISP) Supported – 1.8V ISP Using IEEE 1532 (JTAG) Interface – Boundary-scan Testing to IEEE JTAG Std. 1149.