ATF1508SL Datasheet | Atmel

Features - 2nd Generation EE PROM-based plex Programmable Logic Devices - VCCIO of 5.0V or 3.3V with 3.3V Operation being 5V Tolerant - 32 - 256 Macrocells with Enhanced Features - Pin-patible with Industry Standard Devices - Speeds to 5 ns Maximum Pin-to-pin Delay - Registered Operation to 250 MHz Enhanced Macrocells with Logic Doubling™ Features - Bury Either Register or while Using the Other for Output - Dual Independent Feedback Allows Multiple Latch Functions per Macrocell - 5 Product Terms per Macrocell, expandable to 40 per Macrocell with Cascade Logic, Plus 15 more with Foldback Logic - D/T/Latch Configurable Flip-flops plus Transparent Latches - Global and/or per Macrocell Register Control Signals - Global and/or per Macrocell Output Enable - Programmable Output Slew Rate per Macrocell - Programmable Output Open Collector Option per Macrocell - Fast Registered Input from Product Term Enhanced Connectivity - Single Level Switch Matrix for Maximum Routing Options - Up to 40 Inputs per Logic Block Advanced Power Management Features - ITD (Input Transition Detection) Available Individually on Global Clocks, Inputs and I/O for µA Level Standby Current for “L” Versions - Pin-controlled 1 m A Standby Mode - Reduced-power Option per Macrocell - Automatic Power Down of Unused Macrocells - Programmable Pin-keeper Inputs and I/Os Available in mercial and Industrial Temperature Ranges Available in All Popular Packages Including PLCC, PQFP and TQFP EE PROM Technology - 100% Tested - pletely Reprogrammable - 10,000 Program/Erase Cycles - 20 Year Data Retention - 2000V ESD Protection - 200 m A Latch-up Immunity JTAG Boundary-scan Testing Port per IEEE 1149.1-1990 and 1149.1a-1993 - Pull-up Option on JTAG Pins TMS and TDI IEEE 1532 patibility for Fast In-System Programmability (ISP) via JTAG PCI-pliant Security Fuse Feature - ATF15xx SE Family Datasheet ATF1502SE(L) ATF1504SE(L) ATF1508SE(L) ATF1516SE(L) Preliminary - - - - - - - - - Rev. 2401D- PLD-...