ATMEGA103L Datasheet | Atmel

Features - Utilizes the AVR® RISC Architecture - AVR - High-performance and Low-power RISC Architecture - 121 Powerful Instructions - Most Single Clock Cycle Execution - 32 x 8 General Purpose Working Registers + Peripheral Control Registers - Up to 6 MIPS Throughput at 6 MHz - Data and Nonvolatile Program Memory - 128K Bytes of In-System Programmable Flash Endurance: 1,000 Write/Erase Cycles - 4K Bytes Internal SRAM - 4K Bytes of In-System Programmable EEPROM Endurance: 100,000 Write/Erase Cycles - Programming Lock for Flash Program and EEPROM Data Security - SPI Interface for In-System Programming - Peripheral Features - On-chip Analog parator - Programmable Watchdog Timer with On-chip Oscillator - Programmable Serial UART - Master/Slave SPI Serial Interface - Real-time Counter (RTC) with Separate Oscillator - Two 8-bit Timer/Counters with Separate Prescaler and PWM - Expanded 16-bit Timer/Counter System with Separate Prescaler, pare, Capture Modes and Dual 8-, 9-, or 10-bit PWM - Programmable Watchdog Timer with On-chip Oscillator - 8-channel, 10-bit ADC - Special Microcontroller Features - Low-power Idle, Power-save and Power-down Modes - Software Selectable Clock Frequency - External and Internal Interrupt Sources - Specifications - Low-power, High-speed CMOS Process Technology - Fully Static Operation - Power Consumption at 4 MHz, 3V, 25°C - Active: 5.5 m A - Idle Mode: 1.6 m A - Power-down Mode: < 1 µA - I/O and Packages - 32 Programmable I/O Lines, 8 Output Lines, 8 Input...