ATV5000L Datasheet | Atmel

Features Advanced Programmable Logic Device - High Gate Utilization - .. - Flexible Interconnect Architecture - Universal Routing - Flexible Logic Cells - 128 Flip-Flops and 52 Latches - Multiple Flip-Flop Types - Synchronous or Asynchronous Registers - High Speed - 50 MHz Operation - plete Third Party Software Support No Placement, Routing or Layout Software Required - Proven and Reliable High Speed CMOS EPROM Process - - 2000 V ESD Protection 200 m A Latchup Immunity Reprogrammable - Tested 100% for Programmability mercial, Industrial and Military Temperature Grades Block Diagram 52 INPUT LATCHES High Density UV Erasable Programmable Logic Device 8 INPUT PINS UNIVERSAL AND REGIONAL INTERCONNECT 52 LOGIC CELLS (104 FLIP-FLOPS) 52 I/O PINS 24 BURIED CELLS (24 FLIP-FLOPS) Description The Atmel V5000 is an easy to use, high density programmable logic device. Its simple, regular architecture translates into increased utilization and high performance. The ATV5000 has one programmable binatorial logic array. This guarantees easy interconnection of and uniform performance from all nodes. "Sum terms", which are easy to use groupings of AND-OR gates, provide binatorial logic blocks. Sum terms can be wire OR’d together to integrate larger logic blocks. To expand the levels of logic, buried sum terms feed back into the logic array. The 52 I/O pins can each be driven by a register or a sum term. Each I/O pin has an individually enabled input latch. All 128 registers are configurable as D- or T-types without using extra logic gates. Individual sum terms, asynchronous presets, resets and clocks give each flip-flop added flexibility. A direct "clock from pin" option guarantees synchronization and fast clock to output performance. Standard, off-the-shelf third-party software tools and programmers support the ATV5000. This minimizes start-up investment and improves product support. JLCC Chip Carrier Pin Configuration Pin Name IN Pins 2,32,36,66 Pins 1,34,35,68 I/O VCC...