AVR32AP Description
Feature Summary 32-bit load/store AVR32B RISC architecture 15 general-purpose 32-bit registers 32-bit Stack Pointer, Program Counter and Link Register reside in register file Fully orthogonal instruction set Pipelined architecture allows one instruction per clock cycle for most instructions Byte, half-word, word and double word memory access Shadowed interrupt context for INT3 and multiple interrupt priority levels...