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Feature Summary
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32-bit load/store AVR32B RISC architecture 15 general-purpose 32-bit registers 32-bit Stack Pointer, Program Counter and Link Register reside in register file Fully orthogonal instruction set Pipelined architecture allows one instruction per clock cycle for most instructions Byte, half-word, word and double word memory access Shadowed interrupt context for INT3 and multiple interrupt priority levels Privileged and unprivileged modes enabling efficient and secure Operating Systems Full MMU allows for operating systems with memory protection Instruction and data caches Innovative instruction set together with variable instruction length ensuring industry leading code density DSP extention with saturating arithmetic, and a wide variety of multip
AVR32AP Datasheet
