PIO Description
The Parallel Input/Output 1 (PIO1) 32-bit embedded core peripheral.
PIO Key Features
- patible with an Embedded 32-bit ARM7TDMI™ Processor Up to 32 Programmable I/O Lines Interrupt Generation on Event Glitch
- The address takes into account the 2 LSBs [1:0], but the PIO1 macrocell does not decode these bits From host (bridge) To
- Resets all counters and signals Clocked on rising edge of clock Resets all counters and signals Clocked on falling edge