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SMFR-29C516E-31SB - 16 Bit Flow Through EDAC Error Detection And Correction unit

Description

Table 1: Name Pin Description I/O Active Description Buses U1D[0..15] U2D[0..15] ΜD[0..15] ΜC[0..7] Error Flags CERR NCERR 26 25 O O Low Low Correctable Error Uncorrectable Error 53,49..47,45..42,40..37,35..33,28 23..20,18..15,13..10,8..5 59..62,64..67,69..72,74..77 83..86,88..91 I/O I/O

Features

  • D D D D D D D D Very Low Power CMOS 16.
  • Bit operation with 6 or 8 Check Bits Fast Error Detection : 31 ns (max. ) Fast Error Correction : 32 ns (max. ) Corrects all Single.
  • Bit Errors Detects all Double.
  • Bit Errors Detects some Multi.
  • Bit Errors Detects Chip Errors (x1, x4 & x8 RAM Format) D D D D D D D Correctable and Uncorrectable Error Flags Two User Data Buses User to User Transfer and Listening operation High Drive Capability on Buses :.
  • 12.8 mA TTL Comp.

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Full PDF Text Transcription (Reference)

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29C516E 16–Bit Flow–Through EDAC Error Detection And Correction unit 1. Introduction The 29C516E Atmel EDAC is a very low power flow–through 16–bit Error Detection And Correction unit (EDAC) with two user data buses. The EDAC is used in a high integrity system for monitoring and correction of data values coming from the memory space. During a processor write cycle, at each memory location (16–bit width), EDAC calculated checkword (6 or 8–bit width) is added. When performing a read operation from memory, the 29C516E verifies the entire checkword and data combination. It detects and can correct 100% of all the single–bit errors and it detects all double–bit errors. When the 29C516E uses 6–checkbit, it can detect any error on any single 4–bit memory chip.
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