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Features
• High-density, High-performance, Electrically-erasable Complex Programmable Logic Device – 256 Macrocells – 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell – 160, 192, 208 pins – 10 ns Maximum Pin-to-pin Delay – Registered Operation Up To 100 MHz – Enhanced Routing Resources
• Flexible Logic Macrocell – D/T/Latch Configurable Flip-flops – Global and Individual Register Control Signals – Global and Individual Output Enable – Programmable Output Slew Rate – Programmable Output Open Collector Option – Maximum Logic Utilization by Burying a Register within a COM Output
• Advanced Power Management Features – Automatic 3 mA Standby for “L” Version (Maximum) – Pin-controlled 4 mA Standby Mode (Typical) – Programmable Pin-keeper Inputs and I/Os – Reduced-power Feature pe