TS81102G0 Description
The TS81102G0 uses an innovative architecture, including a sampling delay adjust and tunable output levels. It allows users to process the high-speed output data stream down to processor speed and uses the very high-speed bipolar technology (25 GHz NPN cut-off frequency). 2105C BDC 11/03 1 Block Diagram Figure.
TS81102G0 Key Features
- Programmable DMUX Ratio
- 1:4: Data Rate Max = 1 Gsps
- PD (8b/10b) < 4.3/4.7 W (ECL 50Ω output)
- 1:8: Data Rate Max = 2 Gsps
- PD (8b/10b) < 6/6.9 W (ECL 50Ω output)
- 1:16 with 1 TS8388B or 1 TS83102G0B and 2 DMUX
- Parallel Output Mode
- 8-/10-bit
- ECL Differential Input Data
- DataReady or DataReady/2 Input Clock
TS81102G0 Applications
- Stand-alone Delay Adjust Cell for ADCs Sampling Instant Alignment