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TSPC603R - PowerPC 603e RISC Microprocessor Family PID7t-603e

General Description

The PID7t-603e implementation of the PowerPC 603e (renamed after the 603R) is a low-power implementation of the Reduced Instruction Set Computer (RISC) microprocessor PowerPC family.

The 603R is pin-to-pin compatible with the PowerPC 603e and 603P in a Cerquad package.

Key Features

  • Superscalar (3 Instructions per Clock Peak) Dual 16 KB Caches Selectable Bus Clock 32-bit Compatibility PowerPC Implementation On-chip Debug Support Nap, Doze and Sleep Power Saving Modes Device Offered in Cerquad, CBGA 255, HiTCE CBGA 255 and CI-CGA 255 Features Specific to CBGA 255, HiTCE CBGA 255 and CI-CGA 255.
  • 7.4 SPECint95, 6.1 SPECfp95 at 300 MHz (Estimated).
  • PD Typically = 3.5W (266 MHz), Full Operat.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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Features • • • • • • • Superscalar (3 Instructions per Clock Peak) Dual 16 KB Caches Selectable Bus Clock 32-bit Compatibility PowerPC Implementation On-chip Debug Support Nap, Doze and Sleep Power Saving Modes Device Offered in Cerquad, CBGA 255, HiTCE CBGA 255 and CI-CGA 255 Features Specific to CBGA 255, HiTCE CBGA 255 and CI-CGA 255 • 7.4 SPECint95, 6.1 SPECfp95 at 300 MHz (Estimated) • PD Typically = 3.5W (266 MHz), Full Operating Conditions www.DataSheet4U.