Datasheet Summary
Record of Revision Version Revise Date Page Content
0 0.1
22/Jul/2005 16/Aug/2005 18
First draft. Add “(b) In Parallel Data Interface” figure.
8/Sep/2005
03/Nov/2005
A036QN02 V1 only support CCIR-656, serial 8bit. RGB, and TTL 8bit 6-8 Correct I/O description 9-14 Modify register setting and description Delete Note 2 of 3.5.1 18 Delete “The fist line is at 14th that will be display on panel” of 19 note. 22 Add item “Vsync to 1st active line” of 3.5.2.1 24 Add 3-wire serial munication AC timing figure. Add A036QN02 V0 support “CCIR-601, YUV” interface 3 Change panel surface treatment to “Hard Coating 3H” after 4 Dec/ ’05. Add register setting of “parallel RGB data...