Aaron zhang AG1280
The AG1280 devices contain an industrial state-of-the art two-dimensional row- and column-based architecture to implement custom logic. The logic array consists of LBs, with 16 logic slices (LS) in each LB.| Part No. | AG1280 |
|---|---|
| Datasheet | AG1280 Download |
| Manufacturer | Aaron zhang |
| Description | Low power and low cost CPLD |
| Buy | Stock & Price |
GENERAL DESCRIPTION
AG1280 family provides low cost, ultra-low power CPLDs, with density is 1280 Look-Up Tables(LUTs). The devices feature Embedded Block Memory (EBR), Distributed RAM, and Phase Locked Loops (PLLs). The devices are designed for ultra low power and cost while providing programmable solutions for a wide range of applications, especially in consumer and mobile device products.FEATURES
● Low power and low cost CPLD.● Flexible logic architecture based on LUT.
● Ultra-low power, as low as 60μA standby typical Icc (1.2V Vcc).
● Small footprint package for consumer and mobile application.
● Provides PLL per device provide clock multiplication and phase shifting
● 3.3-V, 2.5-V, 1.8-V, 1.5-V LVCMOS and LVTTL standards
● Flexible device configuration through JTAG interface.
● Table 1-1 Shows AG1280 family features Feature LUTs Distributed RAM (Kbits) EBR SRAM (Kbits) Maximum User I/O pins Number of PLLs Package AG1280 1280 10 68 40 1 48-Pin QFN Page 2 of 14 18676796057 Aaron zhang AG1280 - Low power and low cost CPLD Rev1.0 Content
GENERAL DESCRIPTION
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