ABB0205 Datasheet | Abracon Corporation

FEATURES - - - - - - - - - Frequency range 25 ~ 60MHz. Internal phase locked loop will allow spread spectrum modulation on reference clock to pass to the outputs (up to 100k Hz SST modulation). Zero input - output delay. Less than 700 ps device - device skew. Less than 250 ps skew between outputs. Less than 150 ps cycle - cycle jitter. Output Enable function tri-state outputs. 3.3V operation. Available in 8-Pin 150mil SOIC. PIN CONFIGURATION REF CLK2 CLK1 GND CLKOUT CLK4 VDD CLK3 2 3 4 7 6 5 Remark If REF clock is stopped for more than 10us after it has already been provided to the chip, and after power-up, the output clocks will disappear. In that instance, a full power-up reset is required in order to reactivate the output clocks. DESCRIPTION The ABB0205 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input of the PLL. Since the skew between the input and output is less than ± 350 ps, the device acts as a zero delay buffer. BLOCK DIAGRAM CLKOUT CLK1 CLK2 CLK3 CLK4 30332 Esperanza., Rancho Santa Margarita, Ca 92688 Ph: 949-546-8000 Fax: 949-546-8001 .Abracon. 03/21/05 Page 1 .. Low Skew Output Buffer PIN DESCRIPTIONS Name REF 1 CLK2 2 CLK1 2 GND CLK3 2 VDD CLK4 2 CLKOUT 2 Number 1 2 3 4 5 6 7 8 Type I O O P O P O O Description Input reference frequency. Spread spectrum modulation on this signal will be passed to the output (up to 100k Hz SST modulation). Buffered clock output. Buffered clock output. Ground. Buffered clock output. 3.3V Power Supply. Buffered clock output. Buffered clock output. Internal feed back on this pin. Notes: 1: Weak pull-down. 2: Weak pull-down on all outputs. ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS Supply Voltage Input Voltage, dc Output Voltage, dc...