ABX0239 Datasheet | Abracon Corporation

FEATURES - - Selectable 750k Hz to 800MHz range. Low phase noise output (@ 10k Hz frequency offset, -140d Bc/Hz for 19.44MHz, -127d Bc/Hz for 106.25MHz, -125d Bc/Hz for 155.52MHz, 110d Bc/Hz for 622.08MHz). CMOS (ABX0237), PECL (ABX0235 and ABX0238) or LVDS (ABX0239) output. 12 to 25MHz crystal input. No external load capacitor required. Output Enable selector. Selectable 1/16 to 32x frequency multiplier. 3.3V operation. Available in 16-Pin (TSSOP or 3x3mm QFN). PIN CONFIGURATION (Top View) VDD XIN XOUT SEL3^ SEL2^ OE GND GND 1 2 16 15 SEL0^ SEL1^ GND CLKC VDD CLKT GND GND ABX023x - - - - - - - 3 4 5 6 7 8 14 13 12 11 10 9 DESCRIPTION The ABX0235 (PECL with inverted OE), ABX0237 (CMOS), ABX0238 (PECL), and ABX0239 (LVDS) are high performance and low phase noise XO IC chips. They provide phase noise performance as low as - 125d Bc at 1k Hz offset (at 155MHz) and a typical RMS jitter of 4p S RMS ( at 155MHz ). They accept fundamental parallel resonant mode crystals from 12 to 25MHz. SEL0^ / VDD- VDD / GND- XOUT SEL3^ SEL2^ OE 13 14 15 16 SEL1^ 8 7 6 5 GND CLKC VDD CLKT ABX023x 1 2 3 4 BLOCK DIAGRAM SEL OE PLL (Phase Locked Loop) ^: - : Internal pull-up On 3x3 package, ABX0235/38 do not have SEL0 available: Pin 10 is VDD, pin 11 is GND. However, ABX0237/39 have SEL0 (pin 10), and pin 11 is VDD. See pin assignment table for details. OUTPUT ENABLE LOGICAL LEVELS Part # ABX0238 ABX0235 ABX0237 ABX0239 OE 0 (Default) 1 0 1 (Default) State Output enabled Tri-state Tri-state Output enabled XIN...