Datasheet Summary
v5.0
40MX and 42MX FPGA Families
Fe a t ur es
High C apaci t y
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Single-Chip ASIC Alternative 3,000 to 54,000 System Gates Up to 2.5 kbits Configurable Dual-Port SRAM Fast Wide-Decode Circuitry Up to 202 User-Programmable I/O Pins 5.6 ns Clock-to-Out 250 MHz Performance 5 ns Dual-Port SRAM Access 100 MHz FIFOs 7.5 ns 35-Bit Address Decode
- mercial, Military Temperature and MIL-STD-883 Ceramic Packages
- QML Certification
- Ceramic Devices Available to DSCC SMD
E ase of Int egr at io n
- Mixed Voltage Operation (5.0V or 3.3V I/O)
- Synthesis-Friendly Architecture to Support ASIC Design Methodologies
- Up to 100% Resource Utilization and 100% Pin Fixing
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