AGL250 Datasheet | Actel Corporation

Features and Benefits Low Power - - - - - 1.2 V to 1.5 V Core Voltage Support for Low Power Supports Single-Voltage System Operation 5 µW Power Consumption in Flash- Freeze Mode Low-Power Active FPGA Operation Flash- Freeze Technology Enables Ultra-Low Power Consumption while Maintaining FPGA Content - Easy Entry to / Exit from Ultra-Low-Power Flash- Freeze Mode ® Advanced I/O - - - - - - - - - - - 700 Mbps DDR, LVDS-Capable I/Os (AGL250 and above) 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation Bank-Selectable I/O Voltages- up to 4 Banks per Chip Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X1, and LVCMOS 2.5 V / 5.0 V Input1 Differential I/O Standards: LVPECL, LVDS, B-LVDS, and MLVDS (AGL250 and above) I/O Registers on Input, Output, and Enable Paths Hot-Swappable and Cold-Sparing I/Os‡ Programmable Output Slew Rate1 and Drive Strength Weak Pull-Up/-Down IEEE 1149.1 (JTAG) Boundary Scan Test Pin-patible Packages across the IGLOO Family 1 High Capacity - 15 k to 1 Million System Gates - Up to 144 kbits of True Dual-Port SRAM - Up to 300 User I/Os Reprogrammable Flash Technology - - - - 130-nm, 7-Layer Metal, Flash-Based CMOS Process Live-at-Power-Up (LAPU) Level 0 Support Single-Chip Solution Retains Programmed Design When Powered Off Clock Conditioning Circuit (CCC) and PLL In-System Programming (ISP) and Security - Secure ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES) Decryption (except ARM®-enabled IGLOO® devices) via JTAG (IEEE 1532- pliant)1 - Flash Lock® to Secure FPGA Contents - Six CCC Blocks, One with an Integrated PLL - Configurable Phase Shift, Multiply/Divide, Delay Capabilities, and External Feedback - Wide Input Frequency Range (1.5 MHz up to 250 MHz) Embedded Memory - 1 kbit of Flash ROM User Nonvolatile Memory 1 - SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9, and ×18 organizations) 1 - True Dual-Port SRAM (except ×18) High-Perfo...