AGLE3000 Datasheet | Actel Corporation

Features and Benefits Low Power - - - - 1.2 V to 1.5 V Core Voltage Support for Low Power Supports Single-Voltage System Operation Low-Power Active FPGA Operation Flash- Freeze Technology Enables Ultra-Low Power Consumption while Maintaining FPGA Content - Flash- Freeze Pin Allows Easy Entry to / Exit from Ultra-Low Power Flash- Freeze Mode ® Pro (Professional) I/O - - - - - - - - - - - - - 700 Mbps DDR, LVDS-Capable I/Os 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation Bank-Selectable I/O Voltages- Up to 8 Banks per Chip Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X, and LVCMOS 2.5 V / 5.0 V Input Differential I/O Standards: LVPECL, LVDS, B-LVDS, and M-LVDS Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL 2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3 Class I and II I/O Registers on Input, Output, and Enable Paths Programmable Output Slew Rate and Drive Strength Programmable Input Delay Schmitt Trigger Option on Single-Ended Inputs Weak Pull-Up/-Down IEEE 1149.1 (JTAG) Boundary Scan Test Pin-patible Packages across the IGLOO®e Family High Capacity - 600 k to 3 Million System Gates - 108 to 504 kbits of True Dual-Port SRAM - Up to 620 User I/Os Reprogrammable Flash Technology - - - - 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process Live-at-Power-Up (LAPU) Level 0 Support Single-Chip Solution Retains Programmed Design when Powered Off In-System Programming (ISP) and Security - Secure ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES) Decryption via JTAG (IEEE 1532- pliant) - Flash Lock® to Secure FPGA Contents Clock Conditioning Circuit (CCC) and PLL - Six CCC Blocks, Each with an Integrated PLL - Configurable Phase Shift, Multiply/Divide, Delay Capabilities, and External Feedback - Wide Input Frequency Range (1.5 MHz up to 250 MHz) High-Performance Routing Hierarchy - Segmented, Hierarchical Routing and Clock Structure - High-Performance, Low-Skew...