54SXxx Overview
v3.1 54SX Family FPGAs Le a di ng E dg e P er f or m a nc e F ea t u r es 320 MHz Internal Performance 3.7 ns Clock-to-Out (Pin-to-Pin) 0.1 ns Input Set-Up 0.25 ns Clock Skew Sp e ci f ic at ion s 66 MHz PCI CPLD and FPGA Integration Single Chip Solution 100%.
