A1280XL-xxxx
Overview
- Synthesis-Friendly Architecture Supports ASIC Design Methodologies.
- 95-100% Device Utilization using Automatic Place-and-Route Tools.
- Deterministic, User-Controllable Timing Via Timing Driven Software Tools with Up To 100% Pin Fixing.
- IEEE Standard 1149.1 (JTAG) Boundary Scan Testing. I n t eg r a t o r Se r i e s P r o du c t P r of i l e F am i l y 1200XL Device A1225XL 2,500 N/A 231 220 N/A N/A 231 2 83 No A1240XL 4,000 N/A 348 336 N/A N/A 348 2 104 No A1280XL 8,000 N/A 624 608 N/A N/A 624 2 140 No
