ARINC429 Description
.................................................... 2 ARINC 429 Overview .................................................. 2 Core429 Device Requirements ...................................
ARINC429 Key Features
- Supports ARINC Specification 429-16 Configurable up to 16 Rx and 16 Tx Channels Programmable FIFO Depth
- Up to 512 Words Rx and Tx Channels independently Up to 64 Words Programmable Interrupt Generation
- Verilog User Testbenches
- Libero IDE patible VHDL and Verilog
- plete ARINC 429 Rx/Tx Implementation
- Implemented in an APA600 Device Controlled Via an External Terminal Using Core8051 and RS232 Links
- 1, 10, 16, or 20 MHz 12.5 100 kbps Optional 50 kbps Provides Direct CPU Access to Memory Simple Interface to Core8051 ED
- Selectable Data Rate on Each Channel
- Directly Supported within the Actel Libero IDE Synthesis
- Synplicity® ExemplarTM Synopsys® Vital-pliant VHDL Simulators OVI-pliant Verilog Simulators