AX125 Overview
1.5V, 1.8V, 2.5V, 3.3V Mixed Voltage Operation Bank-Selectable I/Os 8 Banks per Chip Single-Ended I/O Standards: LVTTL, LVCMOS, 3.3V PCI, and 3.3V PCI-X Differential I/O Standards:.
AX125 Key Features
- Registered I/Os
- Hot-Swap pliant I/Os (except PCI)
- Programmable Slew Rate and Drive Strength on Outputs
- Programmable Delay and Weak Pull-Up/Pull-Down Circuits on Inputs Embedded Memory
- Independent, Width-Configurable Read and Write Ports
- Programmable Embedded FIFO Control Logic Segmentable Clock Resources Embedded Phase-Locked Loop
- 14-200 MHz Input Range
- Frequency Synthesis Capabilities up to 1 GHz Deterministic, User-Controllable Timing Unique In-System Diagnostic and Deb
- Table 1-1
- Axcelerator Family Product Profile Device Capacity (in Equivalent System Gates) Typical Gates Modules Register (R-cells)
