GENERAL DESCRIPTION
The device is available in windowed ceramic DIP packages, and plastic one time programmable (OTP) PDIP and PLCC packages. Data can be typically accessed in less than 55 ns, allowing high-performance microprocessors to operate without any WAIT states. The device offers separate Output Enable (OE#) and Chip Enable (CE#) controls, thus eliminating bus contention in a multiple bus microprocessor system. AMD’s CMOS process technology provides high speed, low power, and high noise immunity. Typical power consumption is only 125 mW in active mode, and 100 µW in standby mode. All signals are TTL levels, including programming signals. Bit locations may be programmed singly, in blocks, or at random. The device supports AMD’s Flashrite programming algorithm (100 µs pulses), resulting in a typical programming time of 16 seconds. BLOCK DIAGRAM VCC VSS VPP OE# CE# PGM# Output Enable Chip Enable and Prog Logic Y Decoder A0–A16 Address Inputs Output Buffers Data Outputs DQ0–DQ15 Y...
Advanced Micro Devices
