GENERAL DESCRIPTION
A 12.0 V VPP or 5.0 V CC are not required for write or erase operations. The device offers access times of 65, 70, 90, and 120 ns, allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#), and output enable (OE#) controls. The sector sizes are as follows: one 16 Kbyte, two 8 Kb yt e , o ne 2 24 K b yte an d se ven se ct or s o f 256 Kbytes each. The device is available in both top and bottom boot versions. verifies proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm—an internal algorithm th