AM79C873 Datasheet | Advanced Micro Devices

DESCRIPTION The Net PHY-1 device is a physical-layer, single-chip, low-power transceiver for 100BASE-TX, 100BASE-FX, and 10BASE-T operations. On the media side, it provides a direct interface to Fiber Media for 100BASE-FX Fast Ethernet, Unshielded Twisted Pair Category 5 Cable (UTP5) for 100BASE-TX Fast Ethernet, or UTP5/UTP3 Cable for 10BASE-T Ethernet. Through the IEEE 802.3u Media Independent Interface (MII), the Net PHY-1 device connects to the Medium Access Control (MAC) layer, ensuring a high interoperability among products from different vendors. The Net PHY-1 device uses a low-power, high-performance CMOS process. It contains the entire physical layer functions of 100BASE-FX and 100BASE-TX as defined by the IEEE 802.3u standard, including the Physical Coding Sublayer (PCS), Physical Medium Attachment (PMA), 100BASE-TX Twisted Pair Physical Medium Dependent (TP-PMD) sublayer, and a 10BASE-T Encoder/Decoder (ENDEC). The Net PHY-1 device provides strong support for the Auto-Negotiation function utilizing automatic media speed and protocol selection. The Net PHY-1 device incorporates an internal wave-shaping filter to control rise/fall time, eliminating the need for external filtering on the 10/100 Mbps signals. This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. Publication# 22164 Rev: A Amendment/+2 Issue Date: February 1999 Refer to AMD’s Website (.amd.) for the latest information. P R E L I M I N A R Y BLOCK DIAGRAM 25M OSCI LED1-4 TX CGM LED Driver PECL Driver FXTD± 100TXD± 4B/5B Encoder Scrambler Parallel to Serial NRZ to NRZI NRZI to MLT-3 MLT-3 Driver Rise/Fall Time CTL 25M CLK 125M CLK MII Signals MII Interface/ Control 4B/5B Decoder Codegroup...