GENERAL DESCRIPTION
The bus-master architecture provides high data throughput in the system and low CPU and system bus utilization. The PCnet-PCI II controller is fabricated with AMD’s advanced low-power CMOS process to provide low operating and standby current for power sensitive applications. Publication# 19436 Rev. A Issue Date: April 1995 Amendment /+1 This document contains information on a product under development at Advanced Micro Devices, Inc. The information is intended to help you to evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. AMD PRELIMINARY The PCnet-PCI II controller supports automatic configuration in the PCI configuration space. Additional PCnet-PCI II configuration parameters, including the unique IEEE physical address, can be read from an external non-volatile memory (Microwire EEPROM) immediately following system reset. The controller has the capability to automatically select either the AUI port or the Twisted-Pair transceiver.