GENERAL DESCRIPTION
Products are available in windowed ceramic DIP packages as well as plastic one time programmable (OTP) PDIP, TSOP, and PLCC packages. Typically, any byte can be accessed in less than 55 ns, allowing operation with high-performance microprocessors without any WAIT states. The Am27C256 offers separate Output Enable (OE) and Chip Enable (CE) controls, thus eliminating bus contention in a multiple bus microprocessor system. AMD’s CMOS process technology provides high speed, low power, and high noise immunity. Typical power consumption is only 80 mW in active mode, and 100 µW in standby mode. All signals are TTL levels, including programming signals. Bit locations may be programmed singly, in blocks, or at random. The Am27C256 supports AMD’s Flashrite programming algorithm (100 µs pulses) resulting in typical programming time of 4 seconds. BLOCK DIAGRAM VCC VSS VPP Data Outputs DQ0–DQ7 OE CE Output Enable Chip Enable and Prog Logic Y Decoder Output Buffers Y Gating A0–A14 Address Inputs X Decoder 262,144 Bit Cell Matrix 08007H-1 2-32 Publication# 08007 Rev.
Advanced Micro Devices
