AMPAL22V10 Datasheet | Advanced Micro Devices

FINAL ’L: -7/10/15 PAL22V10 Family, Am PAL22V10/A 24-Pin TTL Versatile PAL Device DISTINCTIVE CHARACTERISTICS s As fast as 7.5-ns propagation delay and 91 MHz f MAX (external) s 10 Macrocells programmable as registered or binatorial, and active high or active low to match application needs s Varied product term distribution allows up to 16 product terms per output for plex functions Advanced Micro Devices s Global asynchronous reset and synchronous preset for initialization s Power-up reset for initialization and register preload for testability s Extensive third-party software and programmer support through Fusion PLD partners s 24-Pin SKINNYDIP, 24-pin Flatpack and 28-pin PLCC and LCC packages save space GENERAL DESCRIPTION The PAL22V10 provides user-programmable logic for replacing conventional SSI/MSI gates and flip-flops at a reduced chip count. The PAL22V10 device implements the familiar Boolean logic transfer function, the sum of products. The PAL device is a programmable AND array driving a fixed OR array. The AND array is programmed to create custom product terms, while the OR array sums selected terms at the outputs. The product terms are connected to the fixed OR array with a varied distribution from 8 to 16 across the outputs (see Block Diagram). The OR sum of the products feeds the output macrocell. Each macrocell can be programmed as registered or binatorial, and active high or active low. The output configuration is determined by two fuses controlling two multiplexers in each macrocell. AMD’s Fusion PLD program allows PAL22V10 designs to be implemented using a wide variety of popular industry-standard design tools. By working closely with the Fusion PLD partners, AMD certifies that the tools provide accurate, quality support. By ensuring that thirdparty tools are available, costs are lowered because a designer does not have to buy a plete set of new tools for each device. The Fusion PLD program also greatly reduces design time since a...