MACH110-20 Datasheet | Advanced Micro Devices

DESCRIPTION The MACH110 is a member of AMD’s high-performance EE CMOS MACH 1 family. This device has approximately three times the logic macrocell capability of the popular PAL22V10 without loss of speed. The MACH110 consists of two PAL blocks interconnected by a programmable switch matrix. The two PAL blocks are essentially “PAL22V16” structures plete with product-term arrays and programmable macrocells. The switch matrix connects the PAL blocks to each other and to all input pins, providing a high degree of connectivity between the fully-connected PAL blocks. This allows designs to be placed and routed efficiently. The MACH110 macrocell provides either registered or binatorial outputs with programmable polarity. If a registered configuration is chosen, the register can be configured as D-type or T-type to help reduce the number of product terms. The register type decision can be made by the designer or by the software. All macrocells can be connected to an I/O cell. If a buried macrocell is desired, the internal feedback path from the macrocell can be used, which frees up the I/O pin for use as an input. Publication# 14127 Rev. I Issue Date: May 1995 Amendment /0 BLOCK DIAGRAM I/O0 - I/O15 I0 - I1, I3 - I4 I/O Cells 16 16 2 Macrocells 44 x 70 AND Logic Array and Logic Allocator Switch Matrix 22 44 x 70 AND Logic Array and Logic Allocator Macrocells 16 I/O Cells 16 16 16 I/O16 - I/O31 CLK1/I5, CLK0/I2 14127I-1 MACH110-12/15/20 CONNECTION DIAGRAM Top View PLCC I/O31 I/O30 I/O29 I/O28 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 I/O14 I/O15 GND I/O18 I/O19 VCC I/O12 I/O13 I/O16 I/O17 I/O20 I/O0 GND 2 6 I/O5 I/O6 I/O7 I0 I1 GND CLK0/I2 I/O8 I/O9 I/O10 I/O11 7 8 9 10 11 12 13 14 15 16 17 I/O2...