APL0470 Datasheet | Advanced Semiconductor Business

Plerow APL0470 .. PLL Module Description The plerow TM PLL synthesizer module was designed for use in wireless and wireline systems in a wide range of frequency from 50 MHz to 6 GHz. ASB’s PLL provides exceptionally low spurious and phase noise performance with fast locking time and low current consumption. All products are available in a surface-mount type package. Features ∙ +3 d Bm Output Level at 470 MHz ∙ Channel Step Size : 100 k Hz ∙ 2 nd Harmonic : < - 20d Bc ∙ Spurious Level : < -70d Bc ∙ Lock Time : < 10 ms ∙ 30 m A Current Consumption ∙ Strip-line Resonator Specifications Parameter Frequency Range Output Power Supply Voltage Current Consumption Channel Step Size 2 Harmonics Spurious Level Lock Time Reference Frequency Reference Input Level Phase Noise (C / N) @ 1 k Hz @ 10 k Hz @ 100 k Hz Output Impedance Operating Temp. Range Package Type & Size Ω °C mm -40 d Bc/Hz -80 -105 -120 50 25 SMT, 19.0W×19.0L×5.8H 85 -75 -102 -115 nd Unit MHz d Bm V m A k Hz d Bc d Bc us MHz d Bm Min. 465 1 Typical 470 3 5 23 100 -25 -75 3 10 Max. 475 5 More Information Website: .asb.co.kr E-mail: sales@asb.co.kr Tel: (82) 42-528-7220 Fax: (82) 42-528-7222 ASB Inc., 4th Fl. Venture Town Bldg., 367-17 Goijeong-Dong, Seo-Gu, Daejon 302-716, Korea -20 -70 10 -4 1) Measurement conditions are as follows: T = 25°C, VCC = 5.0 V, Freq. = 335 MHz, 50 ohm system. Outline Drawing Top View Bottom View Pin Configuration Dimension (mm) A 19.0 B 19.0 C 5.8 D 1.5 E 0.5 F 1.75 G 1.35 H 15.0 I 0.9 Tolerance: ± 0.2 D A E F I C B Side View 1/1 .asb.co.kr 1 2 3 4 9 13 15 16 Others CLOCK DATA ENABLE OSC IN VCC (VCO) RF OUT VCP (PLL) LOCK DETECT Ground December...