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UT54ACTS164 - 8-Bit Shift Registers

Download the UT54ACTS164 datasheet PDF. This datasheet also covers the UT54ACS164 variant, as both devices belong to the same 8-bit shift registers family and are provided as variant models within a single manufacturer datasheet.

General Description

The UT54ACS164 and the UT54ACTS164 are 8-bit shift registers which feature AND-gated serial inputs and an asynchronous clear.

The gated serial inputs (A and B) permit complete control over incoming data.

Key Features

  • ‰ AND-gated (enable/disable) serial inputs ‰ Fully buffered clock and serial inputs ‰ Direct clear ‰ 1.2μ CMOS - Latchup immune ‰ High speed ‰ Low power consumption ‰ Single 5 volt supply ‰ Available QML Q or V processes ‰ Flexible package - 14-pin DIP - 14-lead flatpack ‰ UT54ACS164 - SMD 5962-96556 ‰ UT54ACTS164 - SMD 5962-96557.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (UT54ACS164-AeroflexCircuitTechnology.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number UT54ACTS164
Manufacturer Aeroflex Circuit Technology
File Size 236.47 KB
Description 8-Bit Shift Registers
Datasheet download datasheet UT54ACTS164 Datasheet

Full PDF Text Transcription for UT54ACTS164 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for UT54ACTS164. For precise diagrams, and layout, please refer to the original PDF.

Standard Products UT54ACS164/UT54ACTS164 8-Bit Shift Registers Datasheet November 2010 www.aeroflex.com/logic FEATURES ‰ AND-gated (enable/disable) serial inputs ‰ Fully ...

View more extracted text
com/logic FEATURES ‰ AND-gated (enable/disable) serial inputs ‰ Fully buffered clock and serial inputs ‰ Direct clear ‰ 1.2μ CMOS - Latchup immune ‰ High speed ‰ Low power consumption ‰ Single 5 volt supply ‰ Available QML Q or V processes ‰ Flexible package - 14-pin DIP - 14-lead flatpack ‰ UT54ACS164 - SMD 5962-96556 ‰ UT54ACTS164 - SMD 5962-96557 DESCRIPTION The UT54ACS164 and the UT54ACTS164 are 8-bit shift registers which feature AND-gated serial inputs and an asynchronous clear. The gated serial inputs (A and B) permit complete control over incoming data. A low at either input inhibits entry of new data and resets th