Aeroflex UT54ACT74
The UT54ACS74 and the UT54ACTS74 contain two independent D-type positive triggered flip-flops. When Preset and Clear are inactive (high), data at the D input meeting the setup time requirement CLR1 is transferred to the outputs on the positive-going edge of the D1 clock pulse. The devices are characterized over full military temperature range of -55 C to +125 C.| Part No. | UT54ACT74 |
|---|---|
| Datasheet | UT54ACT74 Download |
| Manufacturer |  Aeroflex |
| Description | Radiation-Hardened Dual D Flip-Flops with Clear & Preset |
| Buy | Stock & Price |
FEATURES
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● radiation-hardened CMOS - Latchup immune High speed Low power consumption Single 5 volt supply Available QML Q or V processes Flexible package - 14-pin DIP - 14-lead flatpack PINOUTS 14-Pin DIP Top View CLR1 D1 CLK1 PRE1 Q1 Q1 VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD CLR2 D2 CLK2 PRE2 Q2 Q2
DESCRIPTION
A low level at the Preset or Clear inputs sets or resets the outputs regardless of the levels of the other inputs. Following the hold time interval, data at the D DataSheet4U.com CLK1 input may be changed without affecting the levels at the outputs. FUNCTION TABLE INPUTS PRE L H L H H H CLR H L L H H H L CLK X X X D X X X H L X OUTPUT Q H L H 1 14-Lead Flatpack Top View 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD CLR2 D2 CLK2 PRE2 Q2 Q2 ee DataSh PRE1 Q1 Q1 VSS Q L H H L H Qo 1 LOGIC SYMBOL PRE1 CLK1 D1 CLR1 PRE2 CLK2 D2 CLR2 (4) (3) (2) (1) (10) (11) (12) (13) (9) (8) Q2 Q2 S C1 D1 R (5) (6) Q1 Q1 H L Qo Note: 1. The output levels in this configuration are not guaranteed to meet the minimum levels for VOH if the lows at preset and clear are near VIL maximum.
