FEATURES
q 45ns and 55ns maximum address access time q Asynchronous operation for compatibility with industrystandard 4K x 8/9 dual-port static RAM q CMOS compatible inputs, TTL/CMOS compatible output levels q Three-state bidirectional data bus q Low operating and standby current q Radiation-hardened process and design; total dose irradiation testing to MIL-STD-883 Method 1019 - Total-dose: 1.0E6 rads(Si) - Memory Cell LET threshold: 85 MeV-cm2 /mg q q - Latchup immune (LET >100 MeV-cm2 /mg) QML Q and QML V compliant part Packaging options: - 68-lead Flatpack - 68-pin PGA 5-volt operation Standard Microcircuit Drawing 5962-96845 INTRODUCTION Arbitration schemes are included on the UT7C138/139 to handle situations when multiple processors access the same memory location. Two ports provide independent, asynchronous access for reads and writes to any location in memory. An M/S pin is provided for implementing 16/18-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic.
Aeroflex
