LCK4801 - Low-Voltage HSTL Differential Clock

Description

PCLK0_EN (PULL-UP) PCLK1_EN (PULL-UP) TESTM (PULL-UP) PLLREF_EN (PULL-UP) REF_SEL (PULL-UP) 1 HSTL_CLK (PULL-UP) HSTL_CLK (PULL-UP) PECL_CLK (PULL-UP) PECL_CLK (PULL-UP) (PULL-UP) EXTFB_IN (HSTL) (PULL-DOWN) EXTFB_EN (PULL-UP) EXTFB_OUT (HSTL) SEL[4:0] (PULL-UP) RESET (PULL-UP) PLL_BYPASS (PULL-UP)

Features

s s s s s s Two fully selectable clock inputs. Fully integrated PLL. 336 MHz to 1 GHz output frequencies. HSTL outputs. HSTL and LVPECL reference clocks. 32-pin TQFP package.

Agere Systems

📥 Download Datasheet

Datasheet Details

Part number	LCK4801
Manufacturer	Agere Systems
File Size	160.93 KB
Description	Low-Voltage HSTL Differential Clock
Datasheet	LCK4801 Datasheet
Additional preview pages of the LCK4801 datasheet.

📁 Similar Datasheet

Other Datasheets by Agere Systems

LCK4802 - Low-Voltage PECL Differential Clock
LCK4950 - Low-Voltage PLL Clock Driver
LCK4953 - Low-Voltage PLL Clock Driver

Full PDF Text Transcription

Click to expand full text

Preliminary Data Sheet July 2001 LCK4801 Low-Voltage HSTL Differential Clock General The LCK4801 is a low-voltage, 3.3 V HSTL differential clock synthesizer. The LCK4801 supports two differential HSTL output pairs with frequencies from 336 MHz to 1 GHz. The clock is designed to support single and multiple processor systems that require HSTL differential inputs. The LCK4801 contains a fully integrated PLL (phase-locked loop) which multiplies the HSTL_CLK or PECL_CLK input frequency to match individual processor clock frequencies. The PLL can be bypassed so that the PCLK outputs are fed from the HSTL_CLK or PECL_CLK input for test purposes. All outputs are powered from a 2 V external supply to reduce onchip power consumption. All outputs are HSTL.

Published: Apr 25, 2005 |