Datasheet4U Logo Datasheet4U.com

OR3LP26B - Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface

Datasheet Summary

Description

7 What Is an FPSC?

Features

  • 9 Routing 9 Configuration 9 Boundary Scan 9 More Series 3 Information 9 OR3LP26B Overview 10 Device Layout 10 PCI Local Bus 10 OR3LP26B PCI Bus Core Overview 12 PCI Bus Interface 12 Embedded Core Options/FPGA Configuration 13 PCI Bus Core Detailed.

📥 Download Datasheet

Datasheet preview – OR3LP26B

Datasheet Details

Part number OR3LP26B
Manufacturer Agere Systems
File Size 5.46 MB
Description Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface
Datasheet download datasheet OR3LP26B Datasheet
Additional preview pages of the OR3LP26B datasheet.
Other Datasheets by Agere Systems

Full PDF Text Transcription

Click to expand full text
Data Sheet March 2000 ORCA® OR3LP26B Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface Introduction Lucent Technologies Microelectronics Group has developed a solution for designers who need the many advantages of an FPGA-based design implementation, coupled with the high bandwidth of an industry-standard PCI interface. The ORCA OR3LP26B (a member of the Series 3+ FPSC family) provides a full-featured 33/50/66 MHz, 32-/64-bit PCI interface, fully designed and tested, in hardware, plus FPGA logic for user-programmable functions. s Four internal FIFOs individually buffer both directions of both the Master and Target interfaces: — Both Master FIFOs are 64 bits wide by 32 bits deep. — Both Target FIFOs are 64 bits wide by 16 bits deep.
Published: |